In semiconductor device package assembly, a semiconductor die (also referred to as an integrated circuit (IC) chip or “chip”) may be bonded directly to a packaging substrate. Such die is formed with bumps of solder affixed to its I/O bonding pads. During packaging, the die is “flipped” onto its front surface (e.g., active circuit surface) so that the solder bumps form electrical and mechanical connections directly between the die and conductive metal pads on the packaging substrate. Underfill is generally applied between the gap formed by the solder bumps in order to further secure the die to the packaging substrate. A semiconductor device package of this type is commonly called a “flip chip package.”
In addition, a heat spreader may further attached over the die and packaging substrate to enhance the heat dissipation ability of the flip chip package. A problem with such a flip chip package is that it is subject to different temperatures during the packaging process. For instance, different temperatures arise with the cool down from the solder joining temperature and the underfill curing temperature. As a result, the package is highly stressed due to the different coefficients of thermal expansion (CTE) of the various package and die materials. The high stress experienced by bonded materials during heating and cooling may cause them to warp or crack and cause the package structure to bow.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the disclosure, are simplified for explanatory purposes, and are not drawn to scale.